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Sreekala, K. S.
- Pattern and Position Dependent Gate Leakage and Reduction Technique
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Authors
Affiliations
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
2 School of Technology and Applied Sciences, Mahatma Gandhi University, Regional Centre, IN
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
2 School of Technology and Applied Sciences, Mahatma Gandhi University, Regional Centre, IN
Source
ICTACT Journal on Microelectronics, Vol 1, No 3 (2015), Pagination: 131-135Abstract
The leakage power has become a vital downside in modern VLSI technology, with the advent in the area of high performance chips and portable electronics. Thus it is necessarily to invest more time and effort in designing low power chip without sacrificing its high performance. This paper describes a steady state gate leakage based on position and biasing states. As a basic reference universal gates are selected and compared the gate leakage of conventional NAND and NOR gate using 180nm TSMC technology. It is shown that the overall leakage in a NAND -gate is smaller than in a NOR gate if equal size transistors are used. It also compares the leakage value of proposed leakage reduction techniques with conventional NAND gate. Simulation results shows up to 88% in average gate leakage reduction with modified techniques.Keywords
Leakage Power, Gate Leakage, QMDT, Direct Tunneling.
References
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- Design and Read Stabilityanalysis of 8T Schmitt Trigger Based SRAM
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Authors
Affiliations
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
Source
ICTACT Journal on Microelectronics, Vol 2, No 4 (2017), Pagination: 323-328Abstract
This paper presents an 8T Schmitt Trigger (ST) based SRAM design to improve the read stability and power dissipation of conventional 6T SRAM cell. The ST based SRAM cell incorporates built-in feedback mechanism in order to attain robust read operation. The read stability of the cell is 2.5× higher than that of 6T SRAM cell at 1.8V and it can retain data even at a lower Vmin of 0.3V. Also, power consumption is reduced by 22% compared to 6T SRAM design. The layout drawn using 120nm technology rule shows that the 8T ST SRAM occupies 1.2× higher area compared to 6T SRAM cell. Peripheral circuits for the 8T ST SRAM are introduced. Except the precharge circuit and basic SRAM cells, the remaining part of the circuitry is same for both single bit 6T and 8T ST SRAM array design. The single bit 8T ST SRAM array consumes less power and area in nano-scaled technologies. The proposed design was simulated in Mentor Graphics ELDO using TSMC 180nm technology.Keywords
Low Voltage SRAM, Schmitt Trigger, Read Stability, Read SNM.References
- Yoshinobu Nakagome, Masahi Horiguchi, Takayuki Kawahara and K. Itoh, “Review and Future Prospects of Low-Voltage RAM Circuits”, IBM Journal of Research and Development, Vol. 47, No. 5-6, pp. 525-552, 2003.
- A.J. Bhavnagarwala, X. Tang and J.D. Meindl, “The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability”, IEEE Journal of Solid-State Circuits, Vol. 36, No. 4, pp. 658-665, 2001.
- M.M. Khellah, A. Keshavarzi, D. Somasekhar, T. Karnik and V. De, “Read and Write Circuit Assist Techniques for Improving Vccmin of Dense 6T SRAM Cell”, Proceedings of IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, pp. 185-189, 2008.
- K. Noda, K. Matsui, K. Takeda and N. Nakamura, “A Loadless CMOS Four-Transistor SRAM Cell in a 0.18-μm Logic Technology”, IEEE Transactions on Electron Devices, Vol. 12, No. 12, pp. 2851-2855, 2001.
- I. Carlson, S. Andersson, S. Natarajan and A. Alvandpour, “A High Density, Low Leakage, 5T SRAM for Embedded Caches”, Proceedings of 30th European Solid State Circuits Conference, pp. 215-218, 2004.
- B. Zhai, D. Blaauw, D. Sylvester, and S. Hanson, “A sub-200mV 6T SRAM in 0.13μm CMOS”, Proceedings of International Conference on Solid State Circuits, pp. 332-333, 2007.
- Sherif A. Tawfik and Volkan Kursun, “Low Power and Robust 7T Dual-Vt SRAM Circuit”, Proceedings of International Symposium on Circuits and Systems, pp. 1452-1455, 2008.
- N. Verma and A.P. Chandrakasan, “65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy”, Proceedings of International Conference on Solid State Circuits, pp. 328-329, 2007.
- Zhiyu Liu and Volkan Kursun, “High Read Stability and Low Leakage Cache Memory Cell,” Proceedings of IEEE International Symposium on Circuits and Systems, pp. 2774-2777, 2007.
- Anis Feki et.al., “Sub-Threshold 10T SRAM Bit Cell with Read/Write XY Selection”, Solid-State Electronics, Vol. 106, No. 4, pp. 1-11, 2015.
- Ik Joon Chang, Jae-Joon Kim, Sang Phill Park and Kaushik Roy, “A 32 kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS”, IEEE Journal of Solid-State Circuits, pp. 388-622, 2008.
- Sangeeta Singh and Vikky Lakhmani, “Read and Write Stability of 6T SRAM”, International Journal of Advanced Research in Electronics and Communication Engineering, Vol. 3, No. 5, pp. 569-571, 2014.
- Nahid Rahman and B.P. Singh, “Design of Low Power SRAM Memory using 8T SRAM Cell”, International Journal of Recent Technology and Engineering, Vol. 2, No. 1 , pp. 123-127, 2013.
- S. Thirumala Devi and V.V.K. Raju, “Low Power Process Variation Tolerant Schmitt Trigger Based SRAM”, International Journal of Engineering Research & Technology, Vol. 2, No. 6, pp. 3194-3198, 2013.
- Jaydeep P. Kulkarni and Kaushik Roy, “Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 20, No. 2, pp. 319-332, 2012.
- Maheswary Sreenath and Binu K. Mathew, “Ultra Low Voltage, Low Power, Low Area, Process Variation Tolerant Schmitt Trigger based SRAM Design”, International Journal of Advanced Research in Computer Engineering and Technology, Vol. 2, No. 11, pp. 2817-2827, 2013
- A. Kishore Kumar, D. Somasundareswari, V. Duraisamy and T. Shunbaga Pradeepa, “Design of Low Power 8T Sram with Schmitt Trigger Logic”, Journal of Engineering Science and Technology, Vol. 9, No. 6, pp. 670- 677, 2014.
- R. Sandeep, Narayan T Deshpande and A.R. Aswatha, “Design and Analysis of a New Loadless 4T SRAM Cell in Deep Submicron CMOS Technologies”, Proceedings of 2nd International Conference on Emerging Trends in Engineering and Technology, pp. 155-161, 2009.
- Power and Area Efficient 10T Sram with Improved Read Stability
Abstract Views :169 |
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Authors
Affiliations
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, IN
Source
ICTACT Journal on Microelectronics, Vol 3, No 1 (2017), Pagination: 337-344Abstract
In this paper, a 10T Static Random Access Memory bit cell is proposed to meet design specification for performance, stability, area and power consumption. In every state of SRAM cell designs low power and increased noise margin plays an important role. The conventional 6T SRAM cell is very much prone to noise during read operation. In order to overcome the Read SNM problem in the 6T SRAM cell designers have implemented many other SRAM configurations such as 8T, 9T, 10T. These SRAM cell configurations improve the read stability but increase the power consumption. We proposed a 10T SRAM cell which can solve all these problems by introducing the transmission gate and using stacking effect in the configuration. In this paper different SRAM cells analyzed on the basis of power and read stability and we proposed a 1-bit SRAM memory array using the proposed 10T SRAM bit cell that achieves cell stability, lower power consumption and lesser area. The proposed circuit was implemented in Mentor Graphics Design Architect, simulated using Mentor Graphics ELDO at supply voltage of 1.8V with the help of TSMC 180nm technology. Micro wind is used to draw layout of SRAM cells and peripherals.Keywords
Static Random Access Memory, Static Noise Margin, Read Static Noise Margin, Power Consumption, 10T SRAM.References
- Vasudha Gupta and Mohab Anis, “Statistical Design of the 6T SRAM Bit Cell”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 57, No. 1, pp. 93-103, 2010.
- Evert Seevinck, Frans J.List and Jan Lohstroh, “Static Noise Margin analysis of MOS SRAM cells”, IEEE Journal of Solid-State Circuits, Vol. 22, No. 5, pp. 748-754, 1987.
- Anantha P. Chandrakasan, Samuel Sheng and Robert W. Brodersen, “Low-Power CMOS Digital Design”, IEEE Journal of Solid-State Circuits, Vol. 27, No. 4, pp. 473-483, 1992.
- Satyanand Nalam and Benton H. Calhoun, “5T SRAM with Asymmetric Sizing for Improved Read Stability”, IEEE Journal of Solid-State Circuits, Vol. 46, No. 10, pp. 2437-2442, 2011.
- C.B. Kushwah and S.K. Vishvakarma, “A Single Ended with Dynamic Feedback Control 8T Subthreshold SRAM Cell”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 24, No. 1, pp. 373-377, 2016.
- Vasudha Gupta and Mohab Anis, “Statistical Design of the 6T SRAM Bit Cell”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 57, No. 1, pp. 93-104, 2010.
- Benton H. Calhoun and Anatha P. Chandrakasan, “Static Noise Margin variation for sub-threshold SRAM in 65nm CMOS”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 41, No. 7, pp. 1673-1679, 2006.
- K. Takeda, Y. Hagihara, Y. Aimoto, M. Nomura, Y. Nakazawa, T. Ishii and H. Kobatake, “A Read Static Noise Margin Free SRAM Cell for Low VDD and High Speed Applications”, IEEE Journal of Solid-State Circuits, Vol. 41, No. 1, pp. 113-121, 2006.
- Hiroyuki Yamauchi, “A Discussion on SRAM Circuit Design Trend in Deeper Nanometer- Scale Technologies”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 18, No. 5, pp. 763-773, 2010.
- Do Anh-Tuan, Jeremy Yung Shern Low, Joshua Yung Lih Low, Zhi-Hui Kong, Xiaoliang Tan and Kiat-Seng Yeo, “A 8T Differential SRAM with Improved Noise Margin for Bit-Interleaving in 65nm CMOS”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 58, No. 6, pp. 1252-1263, 2011.
- Kiat-Seng Yeo and Kaushik Roy, “Low- Voltage, Low- Power VLSI Subsystems”, 1st Edition, Mc Graw-Hill, 2009.
- RNM Calculation of 6T SRAM Cell in 32nm Process Node based on Current and Voltage Information
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Authors
Affiliations
1 Department of Electronics, School of Technology and Applied Sciences, Mahatma Gandhi University, Edappally, Kochi – 682024, Kerala, IN
1 Department of Electronics, School of Technology and Applied Sciences, Mahatma Gandhi University, Edappally, Kochi – 682024, Kerala, IN
Source
Indian Journal of Science and Technology, Vol 10, No 29 (2017), Pagination:Abstract
Objectives: This work aims to analyze the the dependency of VDD, T and CR (Cell Ratio) on cell stability in terms of Read Noise Margin (RNM) in 32nm technology by the N- curve and butterfly graphical methods. The advantages of considering both voltage and current information for SRAM cell stability measurement have been reported. Methods/Statistical Analysis: The cell stability calculation of SRAM is a central concern in submicron CMOS process nodes, as they reason for increase in dies variability and voltage scaling. The cell Stability of the SRAM is typically calculated by Static Noise Margin (SNM). As it varies with different operating modes of a cell, a detailed analysis is required. In this article, the RNM of SRAM cell is computed by N curve, which compares with the SNM by bufferfly method. SRAM with PMOS access transistor for improved read stability and low voltage application is also presented. Findings: Results show that proposed SRAM gives 50% cell stability in read mode of operation over conventional SRAM cell for CR=3. Application/Improvements: The typical SRAM bit cell with PMOS access transistor shows improved read stability at low voltage application than standard SRAM cell.Keywords
Butterfly Curve, Cell Ratio, N-Curve, Pull-Up Ratio, Read stability, RNM, SNM, SRAM, Write StabilityFull Text